688 VLSI Testing And Verification
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منابع مشابه
Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection
The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during ...
متن کاملTAN: a packet switched network for VLSI testing
We introduce the idea of using Packet Switched Network as the mode of communication between Automatic Test Equipment and the VLSI Chip under test in a Multi-site ATE architecture. We show that our architecture which we refer to as Test Area Network reduces the complexity and time involved in testing tens of chips at a time. To increase the ATE utilization, we distribute a portion of ATE’s task ...
متن کاملA Hybrid Element Method for Capacitance Extraction in Vlsi Layout Verification System
In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC’s). We present a stand-alone extraction program which we developed for validation and testing p...
متن کاملEfficient polygon enclosure algorithms for device extraction from VLSI layouts
The typical description of a VLSI layout is the geometrical description of masks. Layout verification [4] is the testing of a layout to see if it satisfies design and layout rules. An important problem in layout verification is layout device extraction, which involves detection of capacitors, resistors, transistors etc. from the geometrical description of masks. The layout extraction process st...
متن کاملSpecial Section on Test and Verification of VLSIs
The Fifteenth Asian Test Symposium (ATS’06) and the SeventhWorkshop on RTL and High Level Testing (WRTLT’06) were held in Fukuoka, Japan on November 20th–23rd and 23rd–24th, respectively. Excellent works on state-of-the-art and wide-spread ideas and techniques were presented and discussed in ATS’06, while WRTLT’06 provided more frank discussion focusing on RTL and high level testing. We took th...
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